import os
import sys


INV         = []
DATA_MASTER = [ "data_master" ] 
DATA_SLAVE  = [ "data_slave"  ] 
CFG_SLAVE   = [ "cfg_slave"   ] 
INST_MASTER = [ "inst_master" ] 
INST_SLAVE  = [ "inst_slave"  ] 
DATA_BRIDGE = [ "data_master","data_slave" ] 
INST_BRIDGE = [ "inst_master","inst_slave" ] 

top_module = [
    [ "cce_top",   [
    [ "dfe_core"    , DATA_MASTER , INV         , CFG_SLAVE , ],
    [ "cce_core"    , DATA_MASTER , INST_MASTER , CFG_SLAVE , ],
    [ "inst_tcdm"   , INV         , INST_BRIDGE , INV       , ],
    [ "data_tcdm"   , DATA_BRIDGE , INV         , INV       , ],
    [ "data_agent"  , DATA_BRIDGE , INST_SLAVE  , INV       , ],
    [ "msg_queue"   , DATA_SLAVE  , INV         , INV       , ],
    [ "mem_wrap"    , DATA_SLAVE  , INV         , INV       , ],
    ],],

    [ "riscv_top", [
    [ "riscv_core"  , DATA_MASTER , INST_MASTER , INV       , ],
    [ "riscv_core"  , DATA_MASTER , INST_MASTER , INV       , ],
    [ "flash_cache" , DATA_BRIDGE , INST_SLAVE  , CFG_SLAVE , ],
    [ "flash_ctrl"  , DATA_SLAVE  , INV         , CFG_SLAVE , ],
    [ "psram_ctrl"  , DATA_SLAVE  , INST_SLAVE  , CFG_SLAVE , ],
    [ "inst_tcdm"   , INV         , INST_BRIDGE , INV       , ],
    [ "data_tcdm"   , DATA_BRIDGE , INV         , INV       , ],
    [ "mem_wrap"    , DATA_SLAVE  , INV         , INV       , ],
    [ "aes_engin"   , INV         , INV         , CFG_SLAVE , ],
    [ "udma"        , DATA_MASTER , INV         , CFG_SLAVE , ],
    [ "spi_slave"   , DATA_MASTER , INST_MASTER , INV       , ],
    [ "eth_mac"     , DATA_MASTER , INV         , CFG_SLAVE , ],
    [ "usb1_1"      , DATA_MASTER , INV         , INV       , ],
    [ "apb_perih"   , DATA_SLAVE  , INV         , INV       , ],
    ],],

    [ "analog_top",[
    ],],

    [ "pad_mux" ,  [
    ],],
]
 


def a():
    pass

def ana_file():
    print "|-- UC8066_top"
    for t1_module in top_module:
        print "    |-- " + t1_module[0] 
        if t1_module[1]: 
            for t2_module in t1_module[1]:
                print "        |-- " + t2_module[0] 
                if t2_module[1]:
                    for t3_module in t2_module[1]:
                        print "            |-- " + t3_module
                if t2_module[2]:
                    for t3_module in t2_module[2]:
                        print "            |-- " + t3_module        
                if t2_module[3]:
                    for t3_module in t2_module[3]:
                        print "            |-- " + t3_module                        


    str_topm = []
    with open("./UC8066_top.sv","w") as fp:
        str_lvlx = 0
        str_topm.append("")
        str_topm[0] += "module UC8066_top ()\n"
        for t1_module in top_module:
            str_topm[0] += "\n\n//------------------------------------------------------\n"
            str_topm[0] += t1_module[0] + "\n" + t1_module[0] + "_inst0 (); \n"
            str_lvlx    += 1
            str_topm.append("")
            if t1_module[1]: 
                str_topm.append("")
                str_topm[str_lvlx] += "\n\n"
                str_topm[str_lvlx] += "//------------------------------------------------------\n"
                str_topm[str_lvlx] += "//---                                                ---\n"
                str_topm[str_lvlx] += "//------------------------------------------------------\n"                
                str_topm[str_lvlx] += "module " + t1_module[0] + " ()\n\n"
                for t2_module in t1_module[1]:
                    str_topm[str_lvlx] += t2_module[0] + "\n" + t2_module[0] + "_inst0 ( \n"
                    if t2_module[1]:
                        for t3_module in t2_module[1]:
                            str_topm[str_lvlx] += "    LINT_IF.Master " + t3_module + "\n"
                    if t2_module[2]:
                        for t3_module in t2_module[2]:
                            str_topm[str_lvlx] += "    LINT_IF.Slave  " + t3_module + "\n"
                    if t2_module[3]:
                        for t3_module in t2_module[3]:
                            str_topm[str_lvlx] += "    LINT_IF.Slave  " + t3_module + "\n"
                    str_topm[str_lvlx] += ");\n\n"

                str_topm[str_lvlx] += "\nendmodule"
        str_topm[0] += "\nendmodule"

        for strs in str_topm:
            fp.write(strs)


if __name__ == "__main__":
    ana_file()
